Conventional time-slot interchange switches utilize a data memory and a connection memory to control how data passes through the switch. Examples of time-slot interchange (TSI) switch include those described in U.S. Pat. No. 4,510,597 and U.S. Pat. No. 4,093,827. In particular, the connection memory provides addresses to read data from the data memory so as to control the flow of data from inputs of the TSI switch to outputs of the TSI switch.
A circuit for providing data memory addresses in a TSI switch is illustrated in FIG. 1. In FIG. 1, a connection memory read counter 10 and an MPU address buffer 12 provide address values to a multiplexer 14. The MPU address buffer 12 is provided to allow microprocessor access to the connection memory 22. The multiplexer 14 provides a selected one of the output of the connection memory read counter 10 and the MPU address buffer 12 to a predecoder circuit 16. The predecoder provides an address which is clocked into the register 18 on a first clock cycle. The address stored in the register 18 is decoded by decoder 20 and a read of the connection memory 22 is initiated. The data read from the connection memory is stored in a temporary register 24 for use if a microprocessor access is being performed. The output of the connection memory 22 and the temporary register 24 are provided to the multiplexer 26. The temporary register 24 output, however, is only used on a cycle following a microprocessor tick and is not selected by the multiplexer 26 on two subsequent clock cycles. The multiplexer 26 is, therefore, controlled to select the output of the connection memory 22 on cycles other than the cycle immediately following a microprocessor tick and to select the output of the temporary register 24 on the cycle after a clock tick corresponding to a microprocessor access (a microprocessor tick). The output of the mutliplexer 26 is provided to the mutliplexer 30. The multiplexer 30 also receives the output of the MPU address buffer 12. The multiplexer 30 is controlled to select the output of the MPU address buffer during the microprocessor tick and, otherwise, to select the output of the mutliplexer 26.
During operations when a microprocessor access is not performed, the multiplexer 26 provides the direct output of the connection memory 22 or the output of the temporary register 24 to the multiplexer-30. The multiplexer 32 and the comparator 34 receive the output of the multiplexer 30 which provides either the output of a MPU Address buffer 12 or the selected output of the multiplexer 26. For data memory write operations where a microprocessor access is not performed, the multiplexer 32 provides the output of the data memory counter 28. For data memory read operations where a microprocessor access is not performed, the multiplexer 32 provides the output of multiplexer 30 to the register 40.
The address comparator 34 compares the output of the connection memory 22 and the data memory counter 28 and provides a bank selection value that is stored in the bank register 38. Similarly, the output of the connection memory 22 is provided to the register 40 that provides its contents to the predecoder 36. The predecoder 36 provides a pre-decoded address to the decoder 42. The bank register 38 and the register 40 are both clocked during a second clock cycle which is a next subsequent clock cycle to the first clock cycle during which the register 18 is clocked. Thus, the address decode, the connection memory read access and the address compare take less than one clock cycle.
The output of the register 40 is provided to the predecoder 36 that provides its output to a decoder 42, the output of which is provided to the data memory 44. The bank register 38 output is also provided to the data memory 44 for the read operation. The output of the data memory 44 is provided to a parallel-to-serial converter to provide the output of the TSI switch.
As seen in FIG. 1, the data memory read address generation circuit may be considered as including two pipeline stages 50 and 60. As used herein, the term “pipeline stage” refers to operations that are performed between a clock which initiates operations of a first portion of a circuit and a separate clock that initiates operations of a second portion of the circuit. Thus, a pipeline stage may have a duration from a first clock that initiates operations of the pipeline stage to a second clock that initiations operations of the next subsequent pipeline stage. Operations of the pipeline stage are, therefore, initiated with each occurrence of the clock associated with the pipeline stage and terminated upon each occurrence of the clock of the next subsequent pipeline stage. Thus, in FIG. 1, a first pipeline stage 50 is provided between the register 18 and the bank register 38 and register 40. A second pipeline stage 60 is provided from the bank register 38 and address 40. Thus, the first pipeline stage 50 provides for the read of the connection memory, the address compare and the predecode of the data memory read address. The second pipeline stage 60 provides for the decode of the data memory read address and the read of the data memory.
Furthermore, in the system illustrated in FIG. 1, the clocks of the two pipeline stages are synchronized such that the two pipeline stages have equal duration corresponding to one period of the synchronized clocks.
While the system of FIG. 1 provides for reads of the data memory 44 based on the output of the connection memory 22, as the speed and/or size of the TSI switch increases, the time provided for the operations of any of the particular pipeline stages, such as the first pipeline stage 50, may decrease. Such timing constraints may limit the speed and/or size of the TSI switch. Thus, notwithstanding conventional techniques to provide data memory addresses from a connection memory, such techniques may be insufficient as the speed and/or size of TSI switches increase.